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¡Ú DRAM
KM
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1. Samsung Memory
2. DRAM (4)
3. Organization
1: x1 bit 4: x4 bit 8: x8 bit 16: x16 bit 32: x32 bit
4. Operating Voltage [C: 5V V: 3.3V U: 3.0V Q: 2.5V]
5. Depth
[1: 1M 2: 2M 4: 4M 8: 8M 16: 16M *25: 256Kx16(4MD) *51: 512Kx32(16MD)]
6. Refresh
0: 1K(4MD), 4K(16MD), 8K(64MD),
1: 512(4MD), 2K(16MD), 4K(64MD),
2: 1K(16MD)
7. Mode
0: FP Mode 3: FP(Quad CAS) Mode 4: EDO Mode 5: EDO(QuadCAS)Mode
8. Revision [Blank: 1st Gen. A: 2nd Gen. B: 3rd Gen. C: 4th Gen. D: 5th Gen.]
9. Package Type [J: SOJ K: SOJ (Shrinked PKG) T: TSOP 2 S: TSOP 2
(Shrinked PKG) C: CSP]
10. Test Temperature [Blank: Normal (0~70C) E: Extended temp. (-25~85C)
I: Industrialtemp. (-40~85C)]
11. Power (DC Current) [Blank: Normal L: Low Power with Self Refresh]
12. Speed [4: 40ns 45: 45ns 5: 50ns 55: 55ns 6: 60ns 7: 70ns]
¡Ú SDRAM Component (Include PC100)
KM
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1. Samsung Memory
2. DRAM (4)
3. Organization [4: x4 8: x8 16: x16 32: x32]
4. Feature [S: SDRAM]
5. Density [1: 1M 2: 2M 4: 4M 8: 8M 16: 16M 32: 32M 64: 64M 28: 128M ]
6. Refresh [0: 4K 1: 2K 2: 8K 3: 16K ]
7. # of Banks [2: 2 banks 3: 4 banks ]
8. Interface (VDDQ)
[0: LVTTL (3.3V) 1: SSTL_3 (3.3V) 2: SSTL_2 (2.5V) 3: LVTTL (2.5V) ]
9. Revision [Blank: 1st Gen. A: 2nd Gen. B: 3rd Gen. ]
10. Package Type [T: TSOP II (400mil) B: BGA C: uBGA (CSP) ]
11. Temperature [Blank: Normal (0~70C) E: Extended (-25~85C) I: Industrial
(-40~85C) ]
12. Power (G/F for 3.3V VDD & D/E for 2.5V VDD G: Auto & Self refresh (3.3V)
F: Auto & Self refresh with Low power D: Auto & Self refresh (2.5V)
E: Auto & Self refresh with Low power
13. Min. Cycle Time (Max. Frequency)
[7: 7ns (143MHz)
8: 8ns (125MHz
10: 10ns 100MHz) L: CL3 100MHz H: CL2 & CL3 100MHz ]
¡Ú SDRAM Module (Include PC100)
KM
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1. Samsung Memory
2. Memory Module
3. DIMM Configuration
[3: 8 Byte DIMM (168 & 200pin) 4: 8 Byte SODIMM (144pin) ]
4. Data Bit
[50: x72/ECC w/o PLL+Register DIMM with SPD for 168pin(Intel)
66: x64 Unbuffered DIMM with SPD
74: x72/ECC Unbuffered DIMM with SPD
75: x72/ECC PLL+Register DIMM with SPD for 168pin(JEDEC)
77: x72/ECC PLL+Register DIMM with SPD for 168pin(Intel)
78: x72/ECC PLL+Register DIMM with SPD for 200pin(JEDEC) ]
5. Feature [S: SDRAM ]
6. Density [1: 1M 2: 2M 4: 4M 8: 8M 9: 8M (for 128Mb/512Mb) 16: 16M 17: 16M (for 128Mb/512Mb) 32: 32M 33: 32M (for 128Mb/512Mb) 64: 64M 65: 64M (for 128Mb/512Mb) 28: 128M 29: 128M (for 128Mb/512Mb) ]
7. Refresh, # of Banks in Comp. & Interface
0: 4K/64ms Refresh, 2 Banks & LVTTL
1: 2K/32ms Refresh, 2 Banks & LVTTL
2: 4K/64ms Refresh, 4 Banks & LVTTL
3: 4K/64ms Refresh, 2 Banks & SSTL
4: 4K/64ms Refresh, 4 Banks & STL
5: 8K/64ms Refresh, 4 Banks & LVTTL
6: 16K/128ms Refresh, 4 Banks & LVTTL
8. Composition Component
[0: x4 3: x8 4: x16 5: x32 7: x4 Stack ]
9. Component Revision
[Blank: 1st Gen. A: 2nd Gen. B: 3rd Gen. C: 4th Gen.]
10. Package Type
[T: TSOP II (400mil) B: BGA C: uBGA (CSP) ]
11. PCB Revision & Type
[Blank: 1st 1: 2nd 2: 3rd 3: 4th L: PC66 T:PC100 ]
12. Power
[G: Auto & Self refresh F: Auto & Self refresh with Low power ]
13. Min. Cycle Time (Max. Frequency)
7: 7ns (143MHz)
8: 8ns (125MHz)
0: 0ns (100MHz)
L: CL3 100MHz
H: CL2 & CL3 100MHz ]
¡Ú SIMM
KM
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1. Samsung Memory
2. Module
3. Memory Type & Edge Connector
[1: Flash 2: MASK ROM 3: DRAM DIMM 4: DRAM 8 byte SODIMM 5: Old JEDEC DRAM SIMM 6: SRAM 7: New JEDEC DRAM SIMM 8: ASSP
9: VRAM ]
4. Organization
8/9: x8/x9 bit
32/36: x32/x36 bit
39/40: x39/x40 bit
64/72: x64/x72 bit
144: x144 ]
5. Process & Operating Voltage
[Blank: CMOS 5V V: CMOS 3.3V S: Sync. 3.3V ]
6. Density
[32: 32M 16: 16M 8: 8M 4: 4M 2: 2M 1: 1M 512: 512K 256: 256K ]
7. Refresh
[0: 4K Cycle 1: 2K Cycle 2: 1K Cycle 8: 8K Cycle ]
8. Power Consumption
[0: Normal 2: Low Power & Self Refresh 4: Super Low Power ]
9. Operation & Organization
0: F/P
1: Nibble
2: Static Column
3: Using Quad CAS
4: Using EDO
5: Using EDO & Quad CAS
8: Using Non Memory Logic
9: Using Non Memory Logic & Quad CAS
10. Component Revision
[Blank: None A: 1st Gen. B: 2nd Gen. C: 3rd Gen. ]
11. Package Type
[Blank: SOJ(1st) K: SOJ(2nd) T: TSOP(1st) S: TSOP(2nd) ]
12. PCB Revision
[Blank: None 1: 1st Rev. 2: 2nd Rev. 3: 3rd Rev. ]
13. Number of Components
Blank: More than 7 chips
N: Less than 8 chips
U: Byte wide Base W: Word wide base
14. Only x32 or x33 PCB [V: x32 or x33 PCB ]
15. Lead Finish & Customer
Blank: Solder
G: Gold D: DEC H: HP M: IBM P: Nickel Q: Compaq X: Cambex
16. Speed [5: 50ns 6: 60ns 7: 70ns ]
¡Ú DIMM
KM
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1. Samsung Memory
2. Module
3. Memory Type & Edge Connector
1: Flash
2: MASK ROM
3: DRAM DIMM
4: DRAM 8 byte SODIMM
5: Old JEDEC DRAM SIMM
6: SRAM
7: New JEDEC DRAM SIMM
8: ASSP
9: VRAM ]
4. Data Bit
8/9: x8/x9 bit
32/36: x32/x36 bit
39/40: x39/x40 bit
64/72: x64/x72 bit
66/74: x64/x72 unbuffered DIMM
144: x144 bit ]
5. Mode/Feature & Process & Operating Voltage
[C: F/P, 5V
V: F/P, 3.3V
E: EDO, 5V
F: EDO, 3.3V
W: Window RAM, 5V
S: Sync., 3.3V
G: Sync. Graphic,3.3V
6. Density
[1: 1M 2: 2M 4: 4M 8: 8M 16: 16M 32: 32M ]
7. Refresh
[0: 4K Cycle 1: 2K Cycle 2: 1K Cycle 8: 8K Cycle ]
8. Composition Component
0: x4
1: x4 + x1
2: x4 + x4(Quad CAS)
3: x8
4: x16
5: x16 + x4(Quad CAS)
6: x9 Parity DIMM
7: x18 Parity DIMM
8: x9 ECC DIMM
9: x18 ECC DIMM ]
9. Component Revision
[Blank: None A: 1st Gen. B: 2nd Gen. C: 3rd Gen. ]
10. Package Type & Lead Finish & Customer
[J: SOJ(1st) & Gold K: SOJ(2nd) & Gold
T: TSOP(1st) & Gold S: TSOP(2nd) & Gold ]
11. PCB Revision [Blank: None 1: 1st Rev. 2: 2nd Rev. 3: 3rd Rev. ]
12. Power [Blank: Normal L: Low Power & Self Refresh ]
13. Speed (Refer to #5 Mode/Feature & Process)
1) Using C, V, E, F 5: 50ns 6: 60ns 7: 70ns
2) Using W, S, G 0: 10ns 2: 12ns
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¡Ø 0 : Standard MEM. 3 : EDO MEM.
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¡Ø 6 : 60 ns(³ª³ëÃÊ), 7 : 70 ns, 8 : 80 ns.
¡Ú 168ÇÉ ·¥ ½Äº° ¹æ¹ý(»ï¼º, Çö´ë, LG ·¥ÀÇ °æ¿ì)
»ï¼º 168PIN
KM48S8030BT-GH (8M*08=64M)
KM416S4030BT-G10 (4M*16=64M)
KM48S202CT-GL (2M*08=16M)
Çö´ë 168PIN
HY57V658020ALTC-10P (8M*08=64M)
HY57V198010CTC-10S (2M*08=16M)
LG 168PIN
GM72V66841CT7J (8M*08=64M)
GM72V6641CT-7J (4M*16=64M)